Clock signals within an integrated circuit may not arrive at all registers at the same time. Part of this variation in time in which a clock signal arrives at different times is due to differences in propagation delay, namely, respective delays from a clock source to different placed and routed loads. This is conventionally referred to as clock skew meaning a difference in arrival time of a clock signal to various clock pins. Notably, clock skew sometimes means the maximum difference in arrival time of a clock signal to multiple similarly clocked circuits, such as registers or flip-flops. Clock skew is a barrier to performance enhancement. A well-known formula for determining clock period for a clock signal passing through intermediate logic to a clocked flip-flop is the sum of time delays associated with any intermediate logic, clock skew, jitter, setup time of the flip-flop and clock-to-output time (delay of the clocked circuit; “clk-q”) of the preceding flip-flop.
One approach to limiting clock skew, namely, reducing the variability in clock signal edge arrival times, in programmable logic devices is to use dedicated clock routing resources. Dedicated clock routing resources conventionally include integrated-circuit (“GLOBAL”) routing resources. These GLOBAL routing resources contain balanced buffered resources (“GLOBAL wires”) formed in a tree pattern to registers of an integrated circuit, such that a clock edge arrives at the same time at all such registers, such as flip-flops, when routed using these GLOBAL routing resources. Clock signals from source to load only using only dedicated clock resources are conventionally referred to as “global clock signals.”
Dedicated clock routing resources conventionally have equivalent buffering with respect to resistance-capacitance (“RC”) delay. Furthermore, clock trees, such as an H-tree, are conventionally balanced, such that delay from a clock source to a similarly positioned load pin of a clock tree is approximately the same. A delay calculator may be used to determine an RC delay calculation for a tree from a clock source to each load pin, for example using RC tree based Penfield-Rubinstein, Elmore or other known delay calculation.
Notably, for programmable logic devices, a general routing fabric, other than dedicated clock resources, may be used for propagating clock signals in order to instantiate a circuit design. This use of general routing fabric may be due to a limited availability of GLOBAL resources. Clock signals distributed using such general routing resources are conventionally referred to as “local clock signals.”
The general routing fabric may be used to propagate clock signals, because it is programmable and allows for the formation of one or more communication paths between two circuit blocks, for example, two configurable logic blocks of the programmable logic device. Interconnections between blocks are composed of a two-layer grid of metal segments. Specially designed pass transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices in order to implement the necessary connections to form the communication path(s).
Such general routing fabric may include wires that extend at least approximately the longitudinal dimension (“HLONG wire” or “HLONG”) and lateral dimension (“VLONG wire” or “VLONG”) of the programmable logic device, and may include longitudinal and lateral wires that do not extend approximately the longitudinal and lateral dimensions of the programmable logic device. For example, there are half length HLONG and VLONG wires, namely, “HHLONG wires” and “VHLONG wires”, or “HHLONGS” and “VHLONGS”, respectively, that extend approximately half the distance of the longitudinal and lateral distances of the programmable logic.
In order to reduce clock skew for “local clock signals”, a template or a pattern based approach is used by CAD tools. For example, for every load pin of a local clock signal uses the same pattern of wires, such as HLONG, followed by HHLONG, followed by VLONG, followed by VHLONG, followed by a clock pin. Because the same pattern is used for all the load pins of a clock signal, the delay of such a clock signal to all such load pins is conventionally substantially consistent. However, such general routing fabric conventionally has greater variability with respect to RC values than dedicated clock resources. This RC value variability can lead to an increase in clock skew even with the use of pattern or template routing. Notably, conventionally general routing resources are not made in the highest level(s) of integrated circuit metal layer(s) and are not balanced, such as in a tree pattern, like global resources. As a result, resistance of wires leads to higher and higher delay as a clock signal travels farther away from a clock source. So, for example, two sets of clock load pins which are sourced from an HLONG wire with different distances from the same sourcing PIP, conventionally will have different delays due to use of such an HLONG wire.
Accordingly, it would be both desirable and useful to provide means for reducing clock skew for designs instantiated in a programmable logic device.